verilog HDLBits刷题[Finite State Machines]“Exams/ece241 2013 q8”---Q8：Design a Mealy FSM

1、题目Implement aMealy-type finite state machine that recognizes the sequence 101 on an input signal namedx. Your FSM should have an output signal,z, that is asserted to logic-1 when the 101 sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.2、分析设计一个Mealy型有限状态机识别输入信号x上的101序列识别到该序列时输出z1同时该状态机有低有效的异步复位。10101这样bit1和bit3重合了算两个序列。四个状态或者 三个状态3、代码module top_module ( input clk, input aresetn, // Asynchronous active-low reset input x, output z ); parameter IDEL0,BIT11,BIT22,BIT33; reg [2:0]state,next_state; always(posedge clk,negedge aresetn)begin if(!aresetn) stateIDEL; else statenext_state; end always(*)begin next_stateIDEL; case(state) IDEL:next_statex?BIT1:IDEL; BIT1:next_statex?BIT1:BIT2; BIT2:next_statex?BIT3:IDEL; BIT3:next_statex?BIT1:BIT2; default:; endcase end assign z(stateBIT2)x; endmodule 或者只有三个状态 module top_module ( input clk, input aresetn, // Asynchronous active-low reset input x, output z ); parameter IDEL0,BIT11,BIT22; reg [2:0]state,next_state; always(posedge clk,negedge aresetn)begin if(!aresetn) stateIDEL; else statenext_state; end always(*)begin next_stateIDEL; case(state) IDEL:next_statex?BIT1:IDEL; BIT1:next_statex?BIT1:BIT2; BIT2:next_statex?BIT1:IDEL; default:; endcase end assign z(stateBIT2)x; endmodule4、结果