verilog HDLBits刷题[Finite State Machines]“Fsm serialdata”---Serial receiver and datapath

1、题目See also: Serial receiverNow that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and is dont-care otherwise.Note that the serial protocol sends theleastsignificant bit first.2、分析8bit数据低位先出✅ case (next_state)【采样时机正确】周期 T0stateSTART组合逻辑中next_stateDATA1 clk 上升沿 state 更新为 DATA1 检测 next_stateDATA1 → 锁存此刻 in第 1 位数据module top_module( input clk, input in, input reset, // Synchronous reset output [7:0] out_byte, output done ); // parameter IDEL5d0,START5d1,DATA15d2,DATA25d3,DATA35d4,DATA45d5,DATA55d6,DATA65d7,DATA75d8,DATA85d9,WAIT_STOP5d10,STOP5d11; reg [4:0]state,next_state; reg [7:0]out_byte_r; always(posedge clk) if(reset) stateIDEL; else statenext_state; always(*)begin next_stateIDEL; case(state) IDEL:next_statein?IDEL:START; START:next_stateDATA1; DATA1:next_stateDATA2; DATA2:next_stateDATA3; DATA3:next_stateDATA4; DATA4:next_stateDATA5; DATA5:next_stateDATA6; DATA6:next_stateDATA7; DATA7:next_stateDATA8; DATA8:next_statein?STOP:WAIT_STOP; WAIT_STOP:next_statein?IDEL:WAIT_STOP; STOP:next_statein?IDEL:START; default:next_stateIDEL; endcase end always(posedge clk)begin case(next_state)//不是state DATA1:out_byte_r{in,out_byte_r[7:1]}; DATA2:out_byte_r{in,out_byte_r[7:1]}; DATA3:out_byte_r{in,out_byte_r[7:1]}; DATA4:out_byte_r{in,out_byte_r[7:1]}; DATA5:out_byte_r{in,out_byte_r[7:1]}; DATA6:out_byte_r{in,out_byte_r[7:1]}; DATA7:out_byte_r{in,out_byte_r[7:1]}; DATA8:out_byte_r{in,out_byte_r[7:1]}; //default:out_byte_r8d0;//这句加上报错但如果改为default:out_byte_rout_byte_r;则对 endcase end assign done(stateSTOP); assign out_bytedone?out_byte_r:8d0; endmodule